(1) Field of the Invention
This invention relates to electronic devices, especially solution-processed devices, and methods for forming such devices.
(2) Description of the Related Art
Semiconducting conjugated polymer thin-film transistors (TFTs) have recently become of interest for applications in cheap, logic circuits integrated on plastic substrates (C. Drury, et al., APL 73, 108 (1998)) and optoelectronic integrated devices and pixel transistor switches in high-resolution active-matrix displays (H. Sirringhaus, et al., Science 280, 1741 (1998), A. Dodabalapur, et al. Appl. Phys. Lett. 73, 142 (1998)). In test device configurations with a polymer semiconductor and inorganic metal electrodes and gate dielectric layers high-performance TFTs have been demonstrated. Charge carrier mobilities up to 0.1 cm2/Vs and ON-OFF current ratios of 106–108 have been reached, which is comparable to the performance of amorphous silicon TFTs (H. Sirringhaus, et al., Advances in Solid State Physics 39, 101 (1999)).
In PCT/GB00/04934 techniques are disclosed that allow fabrication of polymer TFTs by a combination of direct printing and solution processing. These manufacturing techniques offer the possibility of inherently lower cost than inorganic semiconductor manufacturing techniques based on vacuum deposition and photolithographic patterning, and can be well suited for fabrication of low cost electronic circuits on large areas and flexible substrates.
One of the key factors that determines the performance of a polymer TFT is the parasitic contact resistance associated with the injection of charge carriers from the source electrode into the accumulation layer at the semiconductor-dielectric interface as well as the transport of the exiting charge carriers from the accumulation layer to the drain electrode. A finite contact resistance results in a fraction of the applied source-drain voltage dropping across the contacts and in a corresponding reduction of the transistor current, and the linear field-effect mobility, respectively. This is particularly relevant in the so-called linear regime of the transistor where the source-drain voltage is small compared to the gate voltage. A suppression of the current in the linear regime significantly degrades the switching speed of the TFT. In an active matrix display application, for example, the linear operating regime of the transistor determines the switching speed, as the voltage difference between the signal on the data line, and the voltage on the pixel to be addressed approaches zero.
Several factors may contribute to the source and drain contact resistances.                The conductivity of the conducting material that is in contact with the semiconducting polymer and forms the source and drain contacts.        The existence of insulating layers on the surface of the source-drain contacts, such as unintentional oxide layers.        At most metal-semiconductor interfaces a potential barrier exists. The shape of this potential barrier is determined by the difference between the Fermi energy of the metal and the ionisation potential (p-type semiconductor) and electron affinity (n-type), respectively, the image force experienced by a charge carrier in the semiconductor by image charges on the surface of the metal, as well as by the applied electric field. In normal operation of the TFT this so-called Schottky diode is reverse biased at the source, and forward biased at the drain.        In a device configuration where the source-drain contacts are formed on the same side of the semiconducting layer as the accumulation layer (see FIG. 1(a)) the Schottky potential barrier results in a short region between both the source and drain contacts and the accumulation layer in the channel in which no accumulation is possible, and in which the carrier concentration is low. In this region the current is ultimately limited by space-charge limited bulk conduction.        In a device configuration where the source-drain contacts are formed on the opposite side of the accumulation layer (see FIG. 1(b)) transport needs to occur through unaccumulated bulk of the semiconducting polymer layer. To minimize this contribution to the contact resistance the thickness of the semiconducting polymer film should be as small as possible.        
In any particular device configuration several of the above factors might be contributing to the contact resistance, and the total parasitic contact resistance might be considered to be made up of a series combination of the individual contact resistances associated with the different factors.
One of the techniques that has been applied successfully to minimize contact resistance in inorganic semiconductor devices such as amorphous silicon (a-Si) TFTs is the use of highly-doped p+ and n+ semiconductor contacts. In the so-called inverted-staggered (bottom-gate) configuration of an a-Si TFT, the intrinsic a-Si semiconducting layer is formed directly on top of the SiN dielectric layer. Then a highly doped n+ a-Si layer is deposited followed by the deposition of a metal layer such as Cr. The Cr and n+ a-Si layer are then patterned by photolithography and subsequent wet (Cr) and dry etching (n+ a-Si). In this structure efficient electron injection into the intrinsic a-Si layer is from n+ a-Si source/drain contacts with Cr interconnects. The use of a highly doped semiconducting contact of the same material from which the semiconducting channel is formed minimizes both the height of the potential barrier and the width of any carrier depleted region at the contacts, and results in efficient carrier injection.
For inorganic semiconductor devices formation of the highly doped p+/n+ contacts to the semiconductor is usually associated with additional processing steps such as deposition of a highly doped layer, ion implantation steps and additional patterning steps. For polymer TFTs such processing steps are often difficult to perform, partly because of polymer degradation during ion implantation or solvent compatibility problems associated with photolithographic patterning. Furthermore, in general techniques to perform controlled doping with well-defined doping profiles are not established for polymer semiconductors.